The CDBC are quad cross-couple 3-STATE CMOS. NOR latches, and the CDBC are quad cross-couple STATE CMOS NAND latches. Each latch. Data sheet acquired from Harris Semiconductor. SCHSC – Revised March The CDB and CDB types are supplied in lead hermetic. CD datasheet, CD circuit, CD data sheet: TI – CMOS QUAD 3- STATE R/S LATCHES,alldatasheet, datasheet, Datasheet search site for.
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National Semiconductor CD Series Datasheets. CDBM, CD, CDBC Datasheet.
Any way, take into account that the SNN has been obsolete for 25 years, its not a good idea to datasheeh consider that part for a new design. Why does this work? Looks like an SR is my only choice here, but my brain is just a drop of the ocean.
MCU, comms module and voltage regulation sections. Historical anecdotes on my other uses for RS latches. Sign up using Email and Password.
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Eatasheet this is not a huge problem to solve and still match my requirements, the resulting design is not as clear as it would be with a single Reset and the density is lower, requiring me to use more ICs. So you may then want to consider another alternative. The CD is indeed the one I have in the design now. No system this complex has shown up on this site.
(PDF) CD4044 Datasheet download
A state change on the inputs would wake the MCU – whereupon it reads the inputs and then goes back to sleep. Enric Blanco 4, 5 11 Post as a guest Name.
(PDF) CD Datasheet PDF Download – CMOS QUAD 3-STATE R/S LATCHES
Never say you are nobody! I am working on a circuit where I need to hold a few signals until my MCU reads them. I think you need to re-evaluate how much power is required by “keeping the interrupts alive”.
Their later comment says the MCU would be sleeping, before you posted your ‘answer’.
As far as possible I want to keep it digital and without any high frequency line anywhere or, better said, well confined in their own “realm”: I had a sync.
However is practically impossible to find good supply of it and even a datasheet. The reason why I was looking at concentrating everything in Hex Latches instead of Quad Latches was to reduce the IC count and, with this, to have a cleaner design of the traces. However the doubt stand. Path-wise, the design difference wouldn’t look enormous, but would still be an improvement: I would disagree, but I may be missing the picture here.
SNN simply has all of its reset inputs internally connected. Thank you all for your help! For this reason is important that the circuit is able to record a state change even if brief without any clock or external intervention.